The configuration of heterogeneous multicore processors such as vector or array processors can be difficult in effectively using memory on the processor and minimize memory utilization outside of the processor. Parallel processing in vector or array processors can be challenging to the mapping of memory and processing functions. Standard programming techniques result in inefficient memory usage, bandwidth usage and slow performance by not optimizing interaction between multiple operations.
Accordingly, systems and methods that enable improved heterogeneous multicore processor programming remains highly desirable.
It will be noted that throughout the appended drawings, like features are identified by like reference numerals.